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S3C2510A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
1.1 OVERVIEW
Samsung's S3C2510A 16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc. To efficiently support those network applications, S3C2510A provides the followings: 16/32-bit ARM940T RISC embedded with 4K-byte I-cache and 4K-byte D-cache, memory controller with 24-bit external address pins, one external bus master with bus request/acknowledge pins, two 10/100 Mbps Ethernet controllers, PCI & PC Card host/agent controller, AAL5 SAR and UTOPIA L1/L2, two port full/low speed USB host with root hub, one port USB function device with transceiver, six general-purpose DMAs, two high-speed UARTs, one console UART, DES and 3DES for IP security, IIC serial interface, interrupt controller, six 32-bit programmable timers, 30-bit watchdog timer, 64 programmable I/O ports, and four PLLs for clock generation. The S3C2510A is developed using an ARM940T core, 0.18um CMOS standard cells and a memory compiler. Its powerful, elegant and fully static design is suitable for various network applications. Also S3C2510A adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture).
1-1
PRODUCT OVERVIEW
S3C2510A
1.2 FEATURES
The following integrated on-chip functions are described in detail in this user's manual: * * * 16/32-bit ARM940T RISC Embedded 4K-byte I-Cache and 4K-byte D-Cache Memory Controller with 24-bit External Address Pins -- 2 Banks of SDRAM for 16/32-bit Bus -- 8 Banks of Flash/ROM/SRAM/External I/O for 8/16/32-bit Bus -- One External Bus Master with Bus Request/Acknowledge Pins Two 10/100 Mbps Ethernet Controllers PCI Host/Agent Controller or CardBus (PCMCIA) Host/Agent Controller -- PCI Host mode: 5 (or more) PCI Slots Interface for PCI Cards -- PC Card Host mode: 1 PC Card Socket Interface for 16-bit PC Card or CardBus PC Card AAL5 SAR and UTOPIA L1/L2 2 Port Full/Low Speed USB HOST with Root Hub. 1 Port Full Speed USB Function with Transceiver Spec. 1.1 Six General-Purpose DMAs Two High-Speed UARTs One Console UART DES and 3DES for IP Security * * * * * IIC Serial Interface Interrupt Controller Six 32-bit Programmable Timers 30-bit Watchdog Timer 64 Programmable I/O Ports -- 8 General-Purpose I/O -- 6 External Interrupt Request -- 6 Timer Output -- 4 External DMA Request -- 4 External DMA Acknowledge -- 21 SAR Signals -- 15 UART Signals Four PLLs for each ARM940T (166MHz), System (133MHz), PCI & PC Card Controller Clock (33/66MHz), USB Host/Device Clock (48MHz), and Ethernet PHY (20/25MHz). CPU Operating Frequency: Up to 166MHz AHB Bus Operating Frequency: Up to 133MHz Package Type: 416 PBGA Core Operating at 1.8V 5 %, -40~85 C I/O Operating at 3.3V 5 %, -40~85 C 3.3V input/output levels, 5V tolerant only for PCI.
o o
* *
*
* * * * * * *
* * * * * *
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S3C2510A
PRODUCT OVERVIEW
1.3 BLOCK DIAGRAM
10/100 Ethernet MAC
DMA
A H B I/F
4KB D-Cache ARM940T (166 MHz) 4KB I-Cache
High Speed UART
10/100 Ethernet MAC
DMA
High Speed UART
AAL5 SAR & Utopia L1/L2
DMA
133 MHz AHB BUS APB Bridge
Interrupt Controller
Console UART
USB Host Controller
DMA
2-bank SDRAM
PCI/PC Card Host/Agent Controller
DMA
Sys. Bus Arbiter
DES/ 3DES
133 MHz APB BUS
I2C
GPIOs
Memory Controller 8-bank Flash/ROM/ SRAM/ Ext I/O REQ/ACK
Six GDMA
WDT
USB 1.1 Function
Six Timers
External Bus Master
Clock Gen. & Reset Drv. with 4 PLLs
10 MHz OSC.
20 MHz or 25 MHz
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C2510A
ARM940T The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-ona-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software. Memory organization Memory system is composed of 8 ROM/SRAM/Flash/Ext I/O banks and 2 SDRAM banks. Each ROM bank is fixed with 16M-byte address range and is supported with multiplexed and non-multiplexed address/data bus capability. Each SDRAM bank is supported with 128 MByte. Two Ethernet Controllers The S3C2510A includes two Ethernet controllers, which enables the user to configure SOHO router, internet gateway, etc. The main features are as follows. -- Buffered DMA (BDMA) engine using burst mode -- BDMA Tx/Rx buffers (256-byte/256-byte) -- MAC Tx/Rx FIFOs (80-byte/16-byte) to support re-transmit after collision without DMA request -- Data alignment logic -- Support for old and new media (compatible with existing 10M-bit/s networks) -- 10/100 Mbps operation to increase price/performance options and to support phased conversions -- Full IEEE 802.3 compatibility for existing applications -- Media Independent interface (MII) or 7-wire interface -- Station management (STA) signaling for external physical layer configuration and link negotiation -- On-chip CAM (21 addresses) -- Full-duplex mode for doubled bandwidth -- Pause operation hardware support for full-duplex flow control -- Long packet mode for specialized environments -- Short packet mode for fast testing -- PAD generation for ease of processing and reduced processing time
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S3C2510A
PRODUCT OVERVIEW
PCI & PC Card Host/Agent Controller S3C2510A's PCI & PC Card Host/Agent Controller complies with the PCI Local Bus Specification rev. 2.2, PC Card Standard Release 7.2, and various design guides. PCI & PC Card Controller connects the ARM940T processor core and local system memory to the PCI bus or CardBus socket. The PCI bus or CardBus uses a 32bit multiplexed, address/data bus, and various control and error signals. Mis-aligned transfers are supported as well as burst transfers at the maximum data rate of 264MB/s @66MHz (132MB/s @33MHz). S3C2510A can function as a PCI(or CardBus) master(initiator) or target(slave), and function as PCI host bridge(or CardBus host bus adapter) referred to as "host mode" or PCI device(or CardBus PC Card) referred to as "agent mode". In host mode, it can be used as host/PCI bridge (or CardBus socket controller) on main board . But in agent mode, it can be used as PCI device on PCI card or CardBus device on CardBus PC Card. The PCI & PC Card Host Controller provides PCI bus arbitration for the S3C2510A and up to five other PCI bus masters (except PCI target-only devices). It can be disabled to allow for external PCI arbiter (if more than five PCI bus masters will be connected). The PCI & PC Card Host Controller has one integrated block for PCI interface and CardBus interface (common silicon) and it supports only one interface as defined by PCI_PCCDM(PC Card Mode) pin. And PCI_HOSTM pin signal forces PCI & PC Card Controller to operate in host mode or agent mode. Each modes can be set as followings. PCI Host Mode PCI Agent Mode CardBus PC Card Host Mode 16-bit PC Card (PCMCIA) Host Mode CardBus PC Card Agent Mode PCI_PCCDM = 0, PCI_HOSTM=1 PCI_PCCDM = 0, PCI_HOSTM=0 PCI_PCCDM = 1, PCI_HOSTM=1, CardBus PC Card is inserted PCI_PCCDM = 1, PCI_HOSTM=1, 16-bit PC Card is inserted PCI_PCCDM = 1, PCI_HOSTM=0
NOTE: Each mode is selected by PCI_PCCDM & PCI_HOSTM pin input and inserted card type
The PCI & PC Card Host/Agent Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented for flow-through operation of PCI & PC Card read/write burst operation. And doorbell and mailbox registers, CLKRUN# central resource control logic, integrated pull-up resistors are also implemented. As a CardBus host mode, it supports only single PC Card slot and generates interface signals to PC Card powerswitch. CardBus Host Controller supports 16-bit PC Card (PCMCIA card) or CardBus PC Card. CardBus Host Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented. As a PCI/CardBus agent mode, it supports independent three address decoders and provides address translation mechanism to map AHB local memory from PCI bus through three address bars and vice-versa. To support power management, it complies with PCI Bus Power Management Interface Specification Rev. 1.1 and PCI Mobile Design Guide Ver. 1.1. And also it supports DMA operation with two-channel dedicated DMA to enhance the performance.
1-5
PRODUCT OVERVIEW
S3C2510A
PCI Host/Agent Controller Features are as Follows -- 32-bit, 33/66 MHz, 5V tolerant, Up to 264M-byte/sec @66MHz -- PCI Local Bus Specification Rev.2.2 compliant -- PCI Bus Power Management Interface Specification Rev.1.1 compliant -- PCI Mobile Design Guide Ver.1.1 compliant -- Mini PCI Specification Rev.1.0 compliant -- Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant -- Supports PCI PME# pin and wake-up by software -- Round-robin PCI bus arbiter supports five external REQ#, GNT# pins -- Two-channel dedicated DMA -- Integrated pull-up resistors CardBus PC Card Host/Agent Controller Features (Common Silicon with PCI) are as Follows -- 32-bit, 33 MHz, 3.3V, Up to 132M-byte/sec -- PC Card Standard Release 7.1 compliant -- PCI Bus Power Management Interface Specification Rev.1.1 compliant -- PCI Mobile Design Guide Ver.1.1 compliant -- Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant -- Single PC Card slot interface with hot insertion and removal -- Interface to 16-bit PC Card (PCMCIA card) or CardBus PC Card -- Interface to PC Card power-switch like TI TPS2211A and MAXIM MAX1602 -- Integrated slew-rate controlled buffers for the difference between PCI and CardBus -- Advanced filtering on card detect lines provide 60 microseconds of noise immunity -- Supports CardBus CSTSCHG pin and Socket Event (Status Changed registers) registers -- Two-channel dedicated DMA -- Integrated pull-up resistors -- Common memory, attribute memory and I/O interface supported for 16-bit PC Card 16-bit PC Card Host Controller Features (Common Silicon with PCI) are as Follows -- PC Card Standard Release 7.1 compliant -- Advanced filtering on card detect lines provide 60 microseconds of noise immunity -- Two-channel dedicated DMA
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S3C2510A
PRODUCT OVERVIEW
AAL5 SAR and UTOPIA L1/L2 The S3C2510A SAR is a powerful, cost-effective solution for providing packet-to-ATM connectivity. Once a data packet is given to the S3C2510A SAR, the packet is translated into cells using either the AAL5 protocol or the null AAL protocol. Then, without further host intervention, the cells are transmitted using selected scheduling algorithms. The host is notified upon completion of the packet transmission. The S3C2510A SAR also receives cells from the PHY devices, reassembles them into packets, and notifies the host when a packet has arrived. All packets are queued in system memory. Misaligned transfers are supported for ease of implementing LANE and MPOA protocols without requiring any packet data movement. VP scheduling is supported, as well as the more common VC scheduling, allowing a mix of Permanent Virtual Path (PVP), Switched Virtual Path (SVP), Permanent Virtual Channel (PVC), and Switched Virtual Channel (SVC) connections. Some key features are as follow: -- CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis -- AAL0 (raw cells) and AAL5 segmentation and reassembly -- Segments and reassembles data up to about 70Mbps via UTOPIA interface -- Generates and verifies CRC-10 for OAM cells and AAL-3/4 cells -- Concurrent OAM cells and AAL5 cells on each active connection -- Simultaneous segmentation and reassembly of up to 32 connection with internal memory and up to 4K connection with external memory -- On chip 8K-byte SRAM for internal connection memory -- CAM for connection number mapping (up to 32 connections) -- Packet sizes up to 64K-byte -- Scatter and gather packet capability for large packets -- Starts of Packet offset available for ease of implementing bridging and routing between different protocols -- Big/little endian mode for packet payload -- Glue-less UTOPIA level 2 interface (up to 7 PHYs). USB Host Controller S3C2510A supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible, USB Rev1.1 compatible, 2 down stream ports. Support for Full/Low Speed USB devices. The S3C2510A USB Host controller complies with OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information. The main features are as follows -- USB specification 1.0 compliant -- Full/Low speed operation support. -- Root hub built in with 2 downstream ports.
1-7
PRODUCT OVERVIEW
S3C2510A
Universal Serial Bus (USB) Function Device The S3C2510A includes a USB controller that enables the customers to implement USB devices for telephony, audio, and other applications. The USB controller is intended for the full-speed signaling rate of 12Mbit/s. Additionally, the S3C2510A USB controller has following features: -- A total of 5 endpoints: 1 control endpoint and 4 data endpoints that can support control, interrupt, bulk transaction. -- Two data endpoints have 32-byte FIFO, two data endpoints have 64-byte FIFO. -- General DMA supported Universal Asynchronous Receiver Transmitter (UART) The S3C2510A has one console-UART and two high-speed UART. Consol UART can be used as system configuration or debug port. Each high-speed UART can be used as modem interface or other high-speed applications. The most important features of high-speed UART are as follows -- Programmable baud rates -- 32-byte Transmit FIFO and 32-byte Receive FIFO -- UART source clock selectable (Internal clock: MCLK2, External clock : EUCLK) -- Auto baud rate detection -- Infra-red (IR) transmit/receive -- Insertion of one or two Stop bits per frame -- Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers -- Parity checking DES/3DES Accelerator The DES Accelerator is a hardware accelerator for execution of the Data Encryption Standard(DES) algorithms as defined in FIPS PUB 46-1, which is equivalent to the Data Encryption Algorithm(DEA) provided in ANSI x3.921981. The main features are as follows -- DES or Triple DES mode -- ECB or CBC mode -- Encryption or decryption support -- General DMA support Six General DMA Channels The S3C2510A has six general DMA channels, which can be used for data transfer between memory and peripherals (memory to peripherals, peripherals to memory) or within memory space (memory to memory). On-chip peripherals with general DMA service are the two high-speed UART, the DES and the USB controller. General DMA can also support four external DMA requests from DMA request pins (xGDMA_Req0 - xGDMA_Req3). General DMA can also support the programmable cycle counts of the external DMA acknowledge signals (xGDMA_Ack0 - xGDMA_Ack3).
1-8
S3C2510A
PRODUCT OVERVIEW
Six Programmable Timer The S3C2510A has six programmable timers. Each timer has its related pin, which is shared with programmable I/O function. Each timer can be programmed two operation mode. One is interval mode and the other is toggle mode. In interval mode, the initial timer output is set to low and it is set to high for 1 cycle time when timeout is reached. therefore the timer output is shaped like pulse wave. In toggle mode, the timer output is toggled when timeout is reached. Hardware Watchdog Timer The S3C2510A includes a watchdog timer, which is capable of generating system reset when the timeout value is reached. The time value is ranged up to 2^30 system clock cycles. The watchdog timer is used to reset and restart the system when a system has failed due to software error or to wrong response of external device. Programmable Interrupt Controller The S3C2510A has one programmable interrupt controller, which arranges the 36 programmable interrupt sources by the programmable priority. The interrupt controller supports 36 maskable interrupt sources, where 30 interrupts are from internal interrupts and 6 interrupts are from external interrupts. The interrupt with the highest priority is reported to the CPU. Programmable I/O Port Controller The S3C2510A has 64 programmable I/O ports, which can be used for another function. If another function is enabled, its I/O functionality is disabled. Six external interrupt request, four external DMA request, four external DMA acknowledge, six timer outputs, 21 SAR signals, and 15 UART signals are multiplexed with I/O function. Each I/O port can be programmed as Input or Output. I C Controller The S3C2510A has IIC controller, which enables the customer to implement a simple and cost effective inter-IC connection. The IIC bus is a two-wire synchronous serial interface consisting of one data (SDA) and one clock (SCL) line. The S3C2510A IIC controller operates in only single master mode.
2
1-9
PRODUCT OVERVIEW
S3C2510A
1.4 S3C2510A PIN LIST AND PAD TYPE
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type Group System Configurations (21) Pin Name XCLK Pin No. T3 I/O Type I Pad Type phic Description S3C2510A PLL Clock Source. If CLKSEL is Low, PLL output clock is used as the system clock. If CLKSEL is high, XCLK is used as the system clock. System clock output. The internal system clock is monitored via HCLKO. If SDRAM is used, this clock should be used SDRAM clock Clock Select for CPU PLL. If CLKSEL is low, CPU PLL clock is used as ARM940T source clock. If high, XCLK (External clock) is used.
HCLKO
M23
O
phbst24
CLKSEL
U1
I
phic
FILTER
R2
AO
poar50_ PLL filter pin for System PLL. abb If the PLL is used, 320pF capacitor should be connected between the pin and ground. phic phic PHY clock frequency select for PHY PLL. 0 = 20MHz 1 = 25MHz Clock Select for PHY PLL If this pin is set to Low, the PHY PLL generates clock depending on PHY_FREQ state. The PHY PLL goes into power down mode with PHY_CLKSEL set to High.
PHY_FREQ PHY_CLKSEL
Y2 U3
I I
PHY_FILTER
T2
AO
poar50_ PLL filter pin for PHY PLL. abb If the PLL is used, 320pF capacitor should be connected between the pin and ground. phob8 PHY clock Out PHY PLL clock output can be monitored by PHY_CLKO. This clock is used as the external PHY source clock.
PHY_CLKO
AD12
O
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S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group System Configurations (21) Pin Name CLKMOD[1] CLKMOD[0] Pin No. AB4 AC2 I/O Type I Pad Type phic Description The CLKMOD pin determines internal clock scheme of S3C2510A. When CLKMOD is "00", the nfast clock mode is defined. In this mode, the same clock is used as CPU clock and system clock. When CLKMOD is "01" or "10", the sync mode is defined. In this mode, the system clock is half frequency of the CPU clock. When CLKMOD is "11", the async clock mode is defined. In this mode, the CPU clock and system clock can operate independently as long as the CPU clock is faster than system clock. In this case, BUS_FREQ[2:0] pins should be 3b'000 to select PCI PLL, 3b'001 to select USB PLL for programmable setting. CPU Clock Frequency Selection.
CPU_FREQ[2] CPU_FREQ[1] CPU_FREQ[0] BUS_FREQ[2] BUS_FREQ[1] BUS_FREQ[0] nRESET
AE1 AD1 AC3 AD2 AB3 AC1 AB2
I
phic
I
phic
System Bus Clock Frequency Selection.
I
phis
Not Reset. NRESET is the global reset input for the S3C2510A and nRESET must be held to "low" for at least 64 clock cycles for digital filtering. Test Mode. The TMODE pin setting is interpreted as follows: 0 = normal operating mode 1 = chip test mode. BIG endian mode select pin. When this pin is set to "0", the S3C2510A operates in litte endian mode. When this pin is set to "1", the S3C2510A operates in big endian mode. PCI(1'b0) or PC Card(1'b1) Mode Select of PCI & PC Card Controller Host (1'b1) or Agent (1'b0) Mode Select of PCI & PC Card Controller
TMODE
AF3
I
phicd
BIG
W3
I
phicd
PCI_PCCDM PCI_HOSTM
AA2 Y3
I I
phic phic
1-11
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Memory Interface (80) Pin Name ADDR[23:0] ADDR[10] Pin No. B14 I/O Type Pad Type O phot20 Description Address bus. The 24-bit address bus covers the full 16 M word address range of each ROM/SRAM /FLASH and external I/O bank. In the SDRAM interface, ADDR[14:13] is always used as bank address of SDRAM devices. If SDRAM devices with 2 internal bank is used, ADDR[13] should be connected to the BA of SDRAM. If SDRAM devices with 4 internal bank is used, ADDR[14:13] should be connected to the BA[1:0] of SDRAM. ADDR[10]/AP is the auto precharge control pin. The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR[10]/AP. External bi-directional 32bit data bus. The S3C2510A supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank. Not chip select strobe for SDRAM. Two SDRAM banks are supported. Not row address strobe for SDRAM. NSDRAS signal is used for both SDRAM banks. Not column address strobe for SDRAM. NSDCAS signal is used for both SDRAM banks. Clock Enable for SDRAM CKE is clock enable signal for SDRAM. Not Write Enable for SDRAM or 16 bit ROM/SRAM. This signal is always used as write enable of SDRAM and is used as write enable of only 16-bit ROM/SRAM/Flash. (That is, It is not enabled for 8 bit Memory)
XDATA[31:0]
B
phbsut20
nSDCS[1] nSDCS[0] nSDRAS
G24 F26 E25
O O
phot20 phot20
nSDCAS
E26
O
phot20
CKE nSDWE/nWE16
L24 F23
O O
phob12 phot20
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S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Memory Interface (80) Pin Name nEWAIT Pin No. K25 I/O Type I Pad Type phicu Description Not External wait signal. This signal is activated when an external I/O device or ROM/SRAM/Flash banks need more access cycles than those defined in the corresponding control register. Not ROM/SRAM/Flash/ External I/O Chip select. The S3C2510A supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks.
nMCS[7] nMCS[6] nMCS[5] nMCS[4] nMCS[3] nMCS[2] nMCS[1] nMCS[0] B0SIZE[1] B0SIZE[0]
J24 H26 H25 J26 K24 J25 K23 K26 AE3 AF2
O
phot20
I
phic
Bank 0 Data Bus Access Size. Bank0 is used for the boot program. You use these pins to set the size of the bank 0 data bus as follows: "01" = Byte, "10" = Half word, "11" = Word, and "00" = reserved. Not output enable. Whenever a memory read access occurs, the nOE output controls the output enable port of the specific memory device. Not write byte enable or DQM for SDRAM Whenever a memory write access occurs, the nWBE output controls the write enable port of the specific memory device. DQM is data input/output mask signal for SDRAM.
nOE
G25
O
phot20
nWBE[3]/nBE/ DQM[3] nWBE[2]/nBE/ DQM[2] nWBE[1]/nBE/ DQM[1] nWBE[0]/nBE/ DQM[0]
F25 H24 G26 H23
O
phot20
1-13
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Memory Interface (80) Pin Name XBMREQ Pin No. M24 I/O Type I Pad Type phicd Description External Bus Master request. An external bus master uses this pin to request the external bus. When it activates the XBMREQ, the S3C2510A drives the state of external bus pins to high impedance. This lets the external bus master take control of the external bus. When it has control, the external bus master assumes responsibity for SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2510A can get the control of the bus and the XBMACK goes "low". External bus Acknowledge. JTAG Test Clock. The JTAG test clock shifts state information and test data into, and out of, the S3C2510A during JTAG test operations. JTAG Test Mode Select. This pin controls JTAG test operations in the S3C2510A. This pin is internally connected pull-up. JTAG Test Data In. The TDI level is used to serially shift test data and instructions into the S3C2510A during JTAG test operations. This pin is internally connected pull-up. JTAG Test Data Out. The TDO level is used to serially shift test data and instructions out of the S3C2510A during JTAG test operations. JTAG Not Reset. Asynchronous reset of the JTAG logic. This pin is internally connected pull-up.
XBMACK TAP Control (5) TCK
L26 AC5
O I
phob8 phic
TMS
AE4
I
phicu
TDI
AF4
I
phicu
TDO
AD4
O
phot12
nTRST
AE5
I
phicu
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S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Ethernet Controller (2) Pin Name MDC Pin No. B1 I/O Type O Pad Type phob12 Description Management Data Clock. The signal level at the MDC pin is used as a timing reference for data transfers that are controlled by the MDIO signal. Management Data I/O. When a read command is being executed, data that is clocked out of the PHY is presented on this pin. When a write command is being executed, data that is clocked out of the controller is presented on this pin for the Physical Layer Entity, PHY. Collision Detected/Collision Detected for 10M. COL is asserted asynchronously with minimum delay from the start of a collision on the medium in MII mode. COL_10M is asserted when a 10-Mbit/s PHY detects a collision. Transmit Clock/Transmit Clock for 10M. The controller drives TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII mode, the PHY samples TXD[3:0] and TX_EN on the rising edge of TX_CLK. For data transfers, TXCLK_10M is provided by the 10M-bit/s PHY. Transmit Data/Transmit Data for 10M. Transmit data is aligned on nibble boundaries. TXD[0] corresponds to the first bit to be transmitted on the physical medium, which is the LSB of the first byte and the fifth bit of that byte during the next clock. TXD_10M is shared with TXD[0] and is a data line for transmitting to the 10M-bit/s PHY. LOOP_10M is shared with TXD[1] and is driven by the loop-back bit in the control register. Transmit Enable/Transmit Enable for 10M. TX_EN provides precise framing for the data carried on TXD[3:0]. This pin is active during the clock periods in which TXD[3:0] contains valid data to be transmitted from the preamble stage through CRC. When the controller is ready to transfer data, it asserts TXEN_10M.
MDIO
C2
B
phbcut12
Ethernet Controller0 (16)
COL_0
C1
I
phis
TX_CLK_0
D2
I
phis
TXD0[3] TXD0[2] TXD0[1]/ LOOP_10M TXD0[0]/ TXD_10M
E4 E2 D1 D3
O
phob12
TX_EN_0
E3
O
phob4
1-15
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Ethernet Controller0 (16) Pin Name TX_ERR_0/ PCOMP_10M Pin No. E1 I/O Type O Pad Type phob4 Description Transmit Error/Packet Compression Enable for 10M. TX_ERR is driven synchronously to TX_CLK and sampled continuously by the Physical Layer Entity, PHY. If asserted for one or more TX_CLK periods, TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data, or delimiter set located somewhere in the frame that is being transmitted. PCOMP_10M is asserted immediately after the packet's DA field is received. PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller (from National Semiconductor). The MAC can be programmed to assert PCOMP if there is a CAM match, or if there is not a match. The RIC (Repeater Interface Controller) uses this signal to compress (shorten) the packet received for management purposes and to reduce memory usage. (See the DP83950 Data Sheet, published by National Semiconductor, for details on the RIC Management Bus.) This pin is controlled by a special register, with which you can define the polarity and assertion method (CAM match active or not match active) of the PCOMP signal. Carrier Sense/Carrier Sense for 10M. CRS is asserted asynchronously with minimum delay from the detection of a nonidle medium in MII mode. CRS_10M is asserted when a 10-Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also uses this signal. Receive Clock/Receive Clock for 10M. RX_CLK is a continuous clock signal. Its frequency is 25 MHz for 100-Mbit/s operation, and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are driven by the PHY off the falling edge of RX_CLK, and sampled on the rising edge of RX_CLK. To receive data, the RXCLK_10 M clock comes from the 10Mbit/s PHY.
CRS_0
F2
I
phis
RX_CLK_0
F4
I
phis
1-16
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Ethernet Controller0 (16) Pin Name RXD0[3] RXD0[2] RXD0[1] RXD0[0]/ RXD_10M Pin No. G1 G2 F1 F3 I/O Type I Pad Type phis Description Receive Data/Receive Data for 10M. RXD is aligned on nibble boundaries. RXD[0] corresponds to the first bit received on the physical medium, which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock. RXD_10M is shared with RXD[0] and it is a line for receiving data from the 10M-bit/s PHY. Receive Data Valid. PHY asserts RX_DV synchronously, holding it active during the clock periods in which RXD[3:0] contains valid data received. PHY asserts RX_DV no later than the clock period when it places the first nibble of the start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV prior to the first nibble of the SFD, then RXD[3:0] carries valid preamble symbols. LINK_10M is shared with RX_DV and used to convey the link status of the 10M-bit/s endec. The value is stored in a status register. Receive Error. PHY asserts RX_ERR synchronously whenever it detects a physical medium error (e.g., a coding violation). PHY asserts RX_ERR only when it asserts RX_DV. Collision Detected/Collision Detected for 10M. Transmit Clock/Transmit Clock for 10M. Transmit Data/Transmit Data for 10M.
RX_DV_0/ LINK_10M
G3
I
phis
RX_ERR_0
H2
I
phisd
Ethernet Controller1 (16)
COL_1
H4
I
phis
TX_CLK_1 TXD1[3] TXD1[2] TXD1[1]/ LOOP_10M TXD1[0]/ TXD_10M TX_EN_1 TX_ERR_1/ PCOMP_10M CRS_1 RX_CLK_1
H1 K2 J1 J2 H3
I O
phis phob12
J3 K1 K4 L2
O O I I
phob4 phob4 phis phis
Transmit Enable/Transmit Enable for 10M. Transmit Error/Packet Compression Enable for 10M. Carrier Sense/Carrier Sense for 10M. Receive Clock/Receive Clock for 10M.
1-17
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group Ethernet Controller1 (16) Pin Name RXD1[3] RXD1[2] RXD1[1] RXD1[0]/ RXD_10M RX_DV_1/ LINK_10M RX_ERR_1 PCI & PC Card Controller - PCI Host Mode (65) PCICLK1 PCICLK2 PCICLK3/ EXT_PCICLK PCIRST#/ EXT_PCIRST# REQ#/REQ#[1] REQ#[2] REQ#[5] REQ#[4] REQ#[3] GNT#/GNT#[1] GNT#[3] GNT#[2] GNT#[5] GNT#[4] Pin No. M1 M2 L1 K3 L3 N2 AA23 AE24 AD18 AE19 AF22 AD21 AC19 AE20 AF21 AC21 AD20 AE21 AD19 AF20 B O(B) O phtbpcicbu PCI bus grant signal phtbpcicb photcicb PCI bus grant signals PCI bus grant signals I I O O B B B I I (B) phis phisd phopcicb phopcicb phtbpcicb phtbpcicb Receive Data Valid. Receive Error. PCI clock output signal 1 PCI clock output signal 2 PCI clock output signal 3 or external PCI clock input PCI reset signal I/O Type I Pad Type phis Description Receive Data/Receive Data for 10M.
phtbpcicbu PCI bus request signal phtipcicbu PCI bus request signals phtbpcicbu PCI bus request signals
1-18
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group PCI & PC Card Controller - PCI Host Mode (65) Pin Name AD[31:0] C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] PAR FRAME# IRDY# TRDY# DEVSEL# STOP# LOCK# PERR# SERR# INTA# PME# CLKRUN# PCI_XCLK AD26 AA26 V26 T24 W23 AA25 AA24 Y26 Y25 Y24 W26 W25 W24 AF19 AE22 L25 AA3 Pin No. I/O Type B B Pad Type phtbpcicb phtbpcicb Description PCI address / data 32-bit lines Command / byte enable 4-bit lines
B B B B B B O(B) B I(BD) I(BD) I (B) B I
phtbpcicb phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu phic
Even parity signal Signal indicating duration of access Signal indicating the master is ready Signal indicating the target is ready Target device selected signal Stop signal for disconnect or retry Lock signal (always pull-up) Parity error report signal System error report signal Level-sensitive Interrupt signal PCI Power Management Event signal PCI clock speed control signal S3C2510A PCI PLL Clock Source. It can be system bus clock if BUS_FREQ[2:0] select PCI clock. Clock Select for PCI PLL. If this pin is low, PCI PLL on. If high, PCI PLL off. PLL filter pin for PCI PLL.
PCI_CLKSEL
AB1
I
phic
PCI_FILTER * * *
R4
AO
poar50_abb
PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). When in PCI host mode (PCI_PCCDM=0, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to PCI host signals as above. Extra 4 pins (PCICVS[2:1], PCICCD[2:1]) are not used in this mode. These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table".
1-19
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group PCI & PC Card Controller - PCI Agent Mode (53) Pin Name EXT_PCICLK EXT_PCIRST# REQ# GNT# IDSEL AD[31:0] C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] PAR FRAME# IRDY# TRDY# DEVSEL# STOP# LOCK# PERR# SERR# INTA# PME# CLKRUN# * * AD26 AA26 V26 T24 W23 AA25 AA24 Y26 Y25 Y24 W26 W25 W24 AF19 AE22 L25 Pin No. AD18 AE19 AF22 AC21 AD21 I/O Type I (B) B O(B) I (B) I B B Pad Type phtbpcicb phtbpcicb phtbpcicbu phtbpcicbu phtipcicbu phtbpcicb phtbpcicb Description External PCI clock input PCI reset signal PCI bus request signal PCI bus grant signal PCI Initialization Device Select signal PCI address / data 32-bit lines Command / byte enable 4-bit lines
B B B B B B I (B) B OD (BD) OD (BD) O(B) O(B)
phtbpcicb phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu
Even parity signal Signal indicating duration of access Signal indicating the master is ready Signal indicating the target is ready Target device selected signal Stop signal for disconnect or retry Lock signal Parity error report signal System error report signal Level-sensitive Interrupt signal PCI Power Management Event signal PCI clock speed control signal
PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). When in PCI agent mode (PCI_PCCDM=0, PCI_HOSTM=0), PCI & PC Card controller pins are mapped to PCI agent (general PCI device) signals as above. Extra 16 pins (PCICLK[2:1], PCIREQ[5:3], PCIGNT[5:2], PCICVS[2:1], PCICCD[2:1], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table".
*
1-20
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group PCI & PC Card Controller - CardBus PC Card Host Mode (63) Pin Name CCLK / EXT_CCLK CRST# / EXT_CRST# CREQ# CGNT# CAD[31:0] C/BE#[3] C/BE#[2] C/BE#[1] C/BE#[0] CPAR CFRAME# CIRDY# CTRDY# CDEVSEL# CSTOP# CBLOCK# CPERR# CSERR# CINT# CSTSCHG CLKRUN# CVS[2] CVS[1] CCD#[2] CCD#[1] VCCD[0] VCCD[1] VPPD_VCC VPPD_PGM PCI_XCLK PCI_CLKSEL PCI_FILTER AD26 AA26 V26 T24 W23 AA25 AA24 Y26 Y25 Y24 W26 W25 W24 AF19 AE22 L25 N25 N24 M26 M25 AE20 AF20 AC19 AD19 AA3 AB1 R4 Pin No. AD18 AE19 AF22 AC21 I/O Type B B I (B) O (B) B B Pad Type phtbpcicb phtbpcicb phtbpcicbu phtbpcicbu phtbpcicb phtbpcicb Description CardBus clock output or external clock input CardBus reset signal CardBus bus request signal CardBus bus grant signal CardBus address / data 32-bit lines Command / byte enable 4-bit lines
B B B B B B O (B) B I (BD) I (BD) I (B) B B I O (B) O O (B) O I I AO
phtbpcicb phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu phbcbcvs phicbccd phtbpcicbu phopcicb phtbpcicbu phopcicb phic phic poar50_abb
Even parity signal Signal indicating duration of access Signal indicating the master is ready Signal indicating the target is ready Target device selected signal Stop signal for disconnect or retry Lock signal (always pull-up) Parity error report signal System error report signal Level-sensitive Interrupt signal CardBus Status Changed signal CardBus clock speed control signal CardBus Voltage Sense signal lines CardBus Card Detect signal lines CardBus Power-Switch VCC control signal CardBus Power-Switch VCC control signal CardBus Power-Switch VPP control signal VCC Voltage (5V/3.3V) CardBus Power-Switch VPP control signal Higher Voltage (12V) S3C2510A PCI PLL Clock Source. Clock Select for PCI PLL. PLL filter pin for PCI PLL.
1-21
PRODUCT OVERVIEW
S3C2510A
* *
PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). When CardBus PC Card is inserted in CardBus PC Card host mode (PCI_PCCDM=1, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to CardBus PC Card host signals as above. Extra 6 pins (PCICLK1, PCICLK2, PCIREQ2, PCIREQ3, PCIGNT2, PCIGNT3) are not used in this mode. These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table". Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group PCI & PC Card Controller - CardBus PC Card Agent Mode (53) Pin Name EXT_CCLK EXT_CRST# CREQ# CGNT# CAD[31:0] CC/BE#[3] CC/BE#[2] CC/BE#[1] CC/BE#[0] CPAR CFRAME# CIRDY# CTRDY# CDEVSEL# CSTOP# CBLOCK# CPERR# CSERR# CINT# CSTSCHG CLKRUN# GWA_EVENT AD26 AA26 V26 T24 W23 AA25 AA24 Y26 Y25 Y24 W26 W25 W24 AF19 AE22 L25 AD21 B B B B B B I (B) B OD (BD) OD (BD) O (B) O (B) I phtbpcicb phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu phtipcicbu Even parity signal Signal indicating duration of access Signal indicating the master is ready Signal indicating the target is ready Target device selected signal Stop signal for disconnect or retry Lock signal Parity error report signal System error report signal Level-sensitive Interrupt signal CardBus Status Changed signal CardBus clock speed control signal External General Wakeup Event signal Pin No. AD18 AE19 AF22 AC21 I/O Type I (B) B O (B) I (B) B B Pad Type phtbpcicb phtbpcicb phtbpcicbu phtbpcicbu phtbpcicb phtbpcicb Description External CardBus clock CardBus reset signal CardBus bus request signal CardBus bus grant signal CardBus address / data 32-bit lines Command / byte enable 4-bit lines
*
* *
PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). When CardBus PC Card is inserted in CardBus PC Card agent mode (PCI_PCCDM=1, PCI_HOSTM=0), PCI & PC Card controller pins are mapped to CardBus PC Card agent signals as above. Extra 16 pins (PCICLK[2:1], PCIREQ[5:3], PCIGNT[5:2], PCICVS[2:1], PCICCD[2:1], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table".
*
1-22
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group PCI & PC Card Controller - 16-bit PC Card (PCMCIA) Host Mode (64) Pin Name PCRESET PCADDR[25:0] PCDATA[15:0] CE#[2] CE#[1] REG# OE# WE# IORD# IOWR# WAIT# READY (IREQ#) INPACK# WP(IOIS16#) BVD[1] (STSCHG#) BVD[2] (SPKR#) VS#[2] VS#[1] CD#[2] CD#[1] VCCD[0] VCCD[1] VPPD_VCC VPPD_PGM U23 T24 AD26 U24 AC21 U26 V25 W24 AF19 AF22 L25 AE22 AD21 N25 N24 M26 M25 AE20 AF20 AC19 AD19 Pin No. AE19 I/O Type O(B) O(B) B O(B) O(B) O(B) O(B) O(B) O(B) I(BD) I(BD) I (B) I (B) I (B) I B I O(B) O O(B) O Pad Type phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtipcicbu phbcbcvs phicbccd phtbpcicbu phopcicb phtbpcicbu phopcicb Description 16-bit PC Card reset signal 16-bit PC Card address lines 16-bit PC Card data lines Card enable signals (even and odd address) Attribute memory select signal Output enable signal of memory read cycles. Write enable signal of memory write cycles I/O read signal of I/O read cycles I/O write signal of I/O write cycles 16-bit PC Card bus cycle wait signal Ready signal of memory interface or Interrupt request signal of I/O interface Input acknowledge signal of I/O read cycles Write protect signal of memory interface or 16bit I/O indicating signal of I/O interface Battery voltage detect 1 signal or Status change interrupt signal Battery voltage detect 2 signal PC Card Voltage Sense signal lines PC Card Card Detect signal lines PC Card Power-Switch VCC control signal PC Card Power-Switch VCC control signal PC Card Power-Switch VPP control signals VCC Voltage (5V/3.3V) PC Card Power-Switch VPP control signals Higher Voltage (12V)
* *
PCI & PC Card controller pins are 69 pins (66 interface signals + 3 PLL signals). When 16-bit PC Card (PCMCIA card) is inserted in PC Card host mode (PCI_PCCDM=1, PCI_HOSTM=1), PCI & PC Card controller pins are mapped to 16-bit PC Card host (PCMCIA host) signals as above. Extra 5 pins (PCICLK[3:2], PCI_XCLK, PCI_CLK_SEL, PCI_FILTER) are not used in this mode. These pins in above table are shared with other pins according to PCI & PC Card controller mode. Refer to "S3C2510A PCI / PC Card Signals Reference Table". PCI & PC Card controller doesn't support 16-bit PC Card agent (PCMCIA card) mode.
* *
1-23
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group SAR & UTOPIA L1/L2 (29) Pin Name UTO_TXAD[2]/GPIO[45] UTO_TXAD[1]/GPIO[44] UTO_TXAD[0]/GPIO[43] UTO_RXAD[2] UTO_RXAD[1] UTO_RXAD[0] UTO_TXD[7]/GPIO[53] UTO_TXD[6]/GPIO[52] UTO_TXD[5]/GPIO[51] UTO_TXD[4]/GPIO[50] UTO_TXD[3]/GPIO[49] UTO_TXD[2]/GPIO[48] UTO_TXD[1]/GPIO[47] UTO_TXD[0]/GPIO[46] UTO_TXSOC/GPIO[54] UTO_TXENB/GPIO[55] UTO_TXCLAV UTO_RXD[7]/GPIO[63] UTO_RXD[6]/GPIO[62] UTO_RXD[5]/GPIO[61] UTO_RXD[4]/GPIO[60] UTO_RXD[3]/GPIO[59] UTO_RXD[2]/GPIO[58] UTO_RXD[1]/GPIO[57] UTO_RXD[0]/GPIO[56] UTO_RXSOC UTO_RXENB UTO_RXCLAV UTO_CLK Pin No. A10 C11 B10 C10 B9 D10 C8 A7 D8 B7 C9 A8 B8 A9 B6 A6 C7 B3 C5 A4 D5 B4 C6 A5 B5 C4 A3 A2 D6 I/O Type O/B Pad Type phbst8 Description TX Address Bus to the ATM PHY / General I/O Ports.
O
phob12
RX Address Bus to the ATM PHY
O/B
phbst8
Transmit Data Bus to the ATM PHY / General I/O Ports
O/B O/B I I/B
phbst8 phbst8 phis phbst8
Start Of Cell Indicator for Transmit Data / General I/O Ports Transmit Data Transfer Enable, Low Active / General I/O Ports Cell Buffer Available for Transmit Data. Receive Data Bus from the ATM PHY / General I/O Ports
I O I O
phis phob8 phis phob8
Start Of Cell Indicator for Receive Data. Receive Data Transfer Enable, Low Active. Cell Buffer Available for Receive Data. Transfer/Receive Interface Byte Clock.
1-24
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group USB Host/Device (11) Pin Name HUSB_DP[1] HUSB_DP[0] HUSB_DN[1] HUSB_DN[0] USB_DP USB_DN HUSB_OvrCurrent[1] HUSB_OvrCurrent[0] USB_XCLK USB_CLKSEL Pin No. AA4 W4 AA1 Y1 W2 W1 V3 V1 N1 M4 I/O Type B B B B I I I Pad Type pbusb pbusb pbusbfs pbusbfs phic phic phic Description Internal USB HOST transceiver Full/Low Speed differential I/O Internal USB HOST transceiver Full/Low Speed differential I/O Internal USB Function Device transceiver Full Speed differential I/O Internal USB Function Device transceiver Full Speed differential I/O USB HOST Over Current S3C2510A USB PLL Clock Source. USB Clock Select. When USB_CLKSEL is '0', USB PLL output is used as the USB clock. When USB_CLKSEL is '1', the USB_XCLK is used as the USB clock.
USB_FILTER
P2
AO
poar50_ Filter for USB PLL abb If the PLL is used, 320pF capacitor should be connected between the pin and ground. phbst8 phob12 phis phbst8 Console UART Receive Data/General I/O Ports Console UART Transmit Data. UART External Clock for UART0/UART1 HUART0 Receive Data. HURXD0 is the HUART0 input signal for receiving serial data. General I/O Port HUART0 Transmit Data. HUTXD0 is the HUART0 output signal for transmitting serial data. General I/O Port Not HUART0 Data Terminal Ready.. This output signals the host (or peripheral) that HUART0 is ready to transmit or receive serial data. General I/O Port
CUART (2) UART (1) HUART0 (7)
CURXD/GPIO[42] CUTXD UCLK HURXD0/GPIO[28]
AD17 AF18 AD15 AE14
I/B O I I/B
HUTXD0/GPIO[29]
AF14
O/B
phbst8
HUnDTR0/GPIO[30]
AD13
O/B
phbst8
1-25
PRODUCT OVERVIEW
S3C2510A
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group HUART0 (7) Pin Name HUnDSR0/GPIO[31] Pin No. AE15 I/O Type I/B Pad Type phbst8 Description Not HUART0 Data Set Ready. This input signals in the UART0 that the peripheral (or host) is ready to transmit or receive serial data General I/O Port Not request to send. This pin output state goes Low or High according to the transmit data is in Tx buffer or Tx FIFO when hardware flow control bit value set to one in HUART0 control register. If Tx buffer or Tx FIFO has data to send, this pin state goes low. If hardware flow control bit is zero, this pin output can be controlled directly by HUART0 control register. General I/O Port Not Clear to send. This input pin function controlled by hardware flow control bit value in HUART0 control register. If hardware flow control bit set to one, HUART0 can transmit the transmitting data only when this pin state is active. General I/O Port Not Data Carrier Detect. This input pin function is determined by hardware flow control bit value in HUART control register. If hardware flow control bit set to one, HUART0 can receive the receiving data only when this pin state is active. General I/O Port UART1 Receive Data / General I/O Port UART1 Transmit Data / General I/O Port Not UART1 Data Terminal Ready/General I/O Port Not UART1 Data Set Ready/General I/O Port Not UART1 Request To Send/General I/O Port
HUnRTS0/GPIO[32]
AD14
O/B
phbst8
HUnCTS0/GPIO[33]
AF15
I/B
phbst8
HUnDCD0/GPIO[34]
AE16
I/B
phbst8
HUART1 (7)
HURXD1/GPIO[35] HUTXD1/GPIO[36] HUnDTR1/GPIO[37] HUnDSR1/GPIO[38] HUnRTS1/GPIO[39]
AF16 AC15 AE17 AD16 AF17
I/B O/B O/B I/B O/B
phbst8 phbst8 phbst8 phbst8 phbst8
1-26
S3C2510A
PRODUCT OVERVIEW
Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued) Group HUART1 (7) Pin Name HUnCTS1/GPIO[40] HUnDCD1/GPIO[41] General Purpose In/Out Ports (including xINT xGDMA_Req xGDMA_Ack TIMER) (28) GPIO[7] GPIO[6] GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0] xINT[5]/GPIO[13] xINT[4]/GPIO[12] xINT[3]/GPIO[11] xINT[2]/GPIO[10] xINT[1]/GPIO[9] xINT[0]/GPIO[8] xGDMA_Req[3]/GPIO[17] xGDMA_Req[2]/GPIO[16] xGDMA_Req[1]/GPIO[15] xGDMA_Req[0]/GPIO[14] xGDMA_Ack[3]/GPIO[21] xGDMA_Ack[2]/GPIO[20] xGDMA_Ack[1]/GPIO[19] xGDMA_Ack[0]/GPIO[18] TIMER[5]/GPIO[27] TIMER[4]/GPIO[26] TIMER[3]/GPIO[25] TIMER[2]/GPIO[24] TIMER[1]/GPIO[23] TIMER[0]/GPIO[22] IC (2) *
2
Pin No. AC17 AE18 AF7 AE7 AF6 AD6 AC6 AE6 AF5 AD5 AE9 AD8 AF8 AC8 AE8 AD7 AF10 AD9 AE10 AF9 AF11 AD10 AE11 AC10 AF13 AC12 AE13 AD11 AF12 AE12 U4 V2
I/O Type I/B I/B B
Pad Type phbst8 phbst8 phbst8
Description Not UART1 Clear To Send/General I/O Port. Not UART1 Data Carrier Detected/General I/O Port. General I/O Ports.
I/B
phbst8
External interrupt requests/General I/O Ports.
I/B
phbst8
External DMA requests for GDMA/General I/O Ports.
O/B
phbst8
External DMA acknowledge from GDMA/General I/O Ports.
O/B
phbst8
TIMER[5:0] Out/General I/O Ports.
SCL SDA
B B
phbcd8 phbcd8
I C serial clock. I C serial data.
2
2
Total Number of Signal Pins = 296
1-27
PRODUCT OVERVIEW
S3C2510A
1.5 S3C2510A PAD TYPE
Table 1-2. S3C2510A PAD Type and Feature Pad Type phic phicd phicu phis phisd poar50_abb phob4 phob8 phob12 phot12 phot20 phbcut12 phbsut20 phbcd8 phbst8 phbst24 pbusb pbusbfs phopcicb I/O Type I I I I I AO O O O O O B B B B B B B O Current Drive - - - - - - 4mA 8mA 12mA 12mA 20mA 12mA 20mA 8mA 8mA 24mA 6mA 6mA Cell Type LVCMOS Level LVCMOS Level LVCMOS Level LVCMOS Schmitt Trigger Level LVCMOS Schmitt Trigger Level Analog output with separate bulk bias Normal Buffer Normal Buffer Normal Buffer Tri-State Buffer Tri-State Buffer LVCMOS Level Tri-State Buffer LVCMOS Schmit trigger level Tri-State Buffer LVCMOS Level Open drain buffer LVCMOS Schmit trigger level Tri-State Buffer LVCMOS Schmit trigger level Tri-State Buffer USB Host Full/Low Speed Buffer USB Function Full Speed Buffer PCI & PC Card output 3.3V Feature 3.3V 3.3V Pull-down resistor 3.3V Pull-up resistor 3.3V 3.3V Pull-down resistor - 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Pull-up resistor 3.3V Pull-up resistor 3.3V 3.3V 3.3V - - - - Slew-Rate Control - - - - - - -
1-28
S3C2510A
PRODUCT OVERVIEW
Table 1-2. S3C2510A PAD Type and Feature (Continued) Pad Type phtbpcicb phtbpcicbu phtbdpcicbu phtipcicbu phbcbcvs phicbccd I/O Type B B BD I B I Current Drive Cell Type PCI & PC Card Bi-directional PCI & PC Card Bi-directional PCI & PC Card Bi-directional OpenDrain PCI & PC Card input CardBus PC Card CVS CardBus PC Card CCD# Feature 5V tolerant 5V tolerant Pull-up resistor 5V tolerant Pull-up resistor 5V tolerant Pull-up resistor 3.3V 3.3V Slew-Rate Control
NOTE: For the detail information about the pad type, see Input/Output Cells of the "STD130/MDL130 0.18um 3.3V Standard Cell Library Data Book" which is produced by Samsung Electronics Co., Ltd, ASIC Team.
1-29
PRODUCT OVERVIEW
S3C2510A
1.6 S3C2510A PCI / PC CARD SIGNALS REFERENCE TABLE
Table 1-3. S3C2510A PCI / PC Card Signals Reference Table Pin Name Ball Grid I/O cell PCI Host Mode 0 1 PCICLK3 / EXT_PCICLK INTA# PCI Agent Mode 0 0 EXT_PCICLK INTA# CardBus PC Card Host Mode 1 1 CCLK / EXT_CCLK CINT# CardBus PC Card Agent Mode 1 0 EXT_CCLK CINT# EXT_CRST# - - - - - - - CGNT# CREQ# CSTSCHG CAD[31] CAD[30] CAD[29] CAD[28] CAD[27] - CAD[26] CAD[25] CAD[24] PCMCIA Host Mode 1 1 READY(IREQ#) PCRESET VPPD_PGM VPPD_VCC VCCD[1] VCCD[0] PCDATA[14] PCADDR[18] PCDATA[2] WE# INPACK# BVD[1] (STSCHG#) PCDATA[10] PCDATA[9] PCDATA[1] PCDATA[8] PCDATA[0] - PCADDR[0] PCADDR[1] PCADDR[2]
PCI_PCCDM AA2 PCI_HOSTM Y3 PCICLK3 PCIINTA PCIRST PCIGNT5 PCIREQ5 PCIGNT4 PCIREQ4 PCIGNT3 PCIREQ3 PCIGNT2 PCIREQ2 PCIGNT1 PCIREQ1 PCIPME PCIAD31 PCIAD30 PCIAD29 PCIAD28 PCIAD27 PCICLK2 PCIAD26 PCIAD25 PCIAD24
phic phic
AD18 phtbpcicb AF19 phtbdpcicb u AE19 phtbpcicb AD19 phopcicb AC19 phtbpcicbu AF20 phopcicb AE20 phtbpcicbu AD20 phtbpcicb AF21 phtbpcicbu AE21 phtbpcicb AD21 phtipcicbu AC21 phtbpcicb AF22 phtbpcicbu AE22 phtbpcicbu AD22 phtbpcicb AC22 phtbpcicb AF23 phtbpcicb AE23 phtbpcicb AD23 phtbpcicb AE24 phopcicb AF24 phtbpcicb AF25 phtbpcicb AE26 phtbpcicb
PCIRST# / EXT_PCIRST# CRST# / EXT_PCIRST# EXT_CRST# GNT#[5] REQ#[5] GNT#[4] REQ#[4] GNT#[3] REQ#[3] GNT#[2] REQ#[2] GNT# / GNT#[1] REQ# / REQ#[1] PME# AD[31] AD[30] AD[29] AD[28] AD[27] PCICLK2 AD[26] AD[25] AD[24] - - - - - - - IDSEL GNT# REQ# PME# AD[31] AD[30] AD[29] AD[28] AD[27] - AD[26] AD[25] AD[24] VPPD_PGM VPPD_VCC VCCD[1] VCCD[0] - - - - CGNT# CREQ# CSTSCHG CAD[31] CAD[30] CAD[29] CAD[28] CAD[27] - CAD[26] CAD[25] CAD[24]
GWA_EVENT BVD[2](SPKR#)
1-30
S3C2510A
PRODUCT OVERVIEW
Table 1-3. S3C2510A PCI / PC Card Signals Reference Table (Continued) Pin Name Ball Grid AD26 AD25 AC26 AC25 AC24 AB26 AB25 AB24 AB23 AA26 I/O cell PCI Host Mode C/BE#[3] AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] C/BE#[2] FRAME# IRDY# PCICLK1 TRDY# DEVSEL# STOP# (Pull-up) PERR# SERR# PAR C/BE#[1] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] PCI Agent Mode C/BE#[3] AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] C/BE#[2] FRAME# IRDY# - TRDY# DEVSEL# STOP# LOCK# PERR# SERR# PAR C/BE#[1] AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] CardBus PC Card Host Mode CC/BE#[3] CAD[23] CAD[22] CAD[21] CAD[20] CAD[19] CAD[18] CAD[17] CAD[16] CC/BE#[2] CFRAME# CIRDY# CCLK CTRDY# CDEVSEL# CSTOP# (Pull-up) CPERR# CSERR# CPAR# CC/BE#[1] CAD[15] CAD[14] CAD[13] CAD[12] CAD[11] CAD[10] CAD[9] CardBus PC Card Agent Mode CC/BE#[3] CAD[23] CAD[22] CAD[21] CAD[20] CAD[19] CAD[18] CAD[17] CAD[16] CC/BE#[2] CFRAME# CIRDY# - CTRDY# CDEVSEL# CSTOP# CBLOCK# CPERR# CSERR# CPAR# CC/BE#[1] CAD[15] CAD[14] CAD[13] CAD[12] CAD[11] CAD[10] CAD[9] PCMCIA Host Mode REG# PCADDR[3] PCADDR[4] PCADDR[5] PCADDR[6] PCADDR[25] PCADDR[7] PCADDR[24] PCADDR[17] PCADDR[12] PCADDR[23] PCADDR[15] PCADDR[16] PCADDR[22] PCADDR[21] PCADDR[20] PCADDR[19] PCADDR[14] WAIT# PCADDR[13] PCADDR[8] IOWR# PCADDR[9] IORD# PCADDR[11] OE# CE#[2] PCADDR[10]
PCICBE3 PCIAD23 PCIAD22 PCIAD21 PCIAD20 PCIAD19 PCIAD18 PCIAD17 PCIAD16 PCICBE2 PCIIRDY PCICLK1 PCITRDY PCISTOP PCILOCK PCIPERR PCISERR PCIPAR PCICBE1 PCIAD15 PCIAD14 PCIAD13 PCIAD12 PCIAD11 PCIAD10 PCIAD9
phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb
PCIFRAME AA25 phtbpcicbu AA24 phtbpcicbu AA23 Y26 Y24 phopcicb phtbpcicbu phtbpcicbu phtbpcicbu
PCIDEVSEL Y25
W26 phtbpcicbu W25 phtbpcicbu W24 phtbdpcicbu W23 V26 V25 V24 U26 U25 U24 U23 T26 phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb
1-31
PRODUCT OVERVIEW
S3C2510A
Table 1-3. S3C2510A PCI / PC Card Signals Reference Table (Continued) Pin Name Ball Grid T25 T24 R26 R25 R24 R23 P26 P25 P24 N26 N25 N24 M26 M25 I/O cell PCI Host Mode AD[8] C/BE#[0] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] - - - - CLKRUN# PCI Agent Mode AD[8] C/BE#[0] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] - - - - CLKRUN# CardBus PC Card Host Mode CAD[8] CC/BE#[0] CAD[7] CAD[6] CAD[5] CAD[4] CAD[3] CAD[2] CAD[1] CAD[0] CVS[2] CVS[1] CCD#[2] CCD#[1] CCLKRUN# CardBus PC Card Agent Mode CAD[8] CC/BE#[0] CAD[7] CAD[6] CAD[5] CAD[4] CAD[3] CAD[2] CAD[1] CAD[0] - - - - CCLKRUN# PCMCIA Host Mode PCDATA[15] CE#[1] PCDATA[7] PCDATA[13] PCDATA[6] PCDATA[12] PCDATA[5] PCDATA[11] PCDATA[4] PCDATA[3] VS#[2] VS#[1] CD#[2] CD#[1] WP(IOIS16#)
PCIAD8 PCICBE0 PCIAD7 PCIAD6 PCIAD5 PCIAD4 PCIAD3 PCIAD2 PCIAD1 PCIAD0 PCICVS2 PCICVS1 PCICCD2 PCICCD1
phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phtbpcicb phbcbcvs phbcbcvs phicbccd phicbccd
PCICLKRUN L25 phtbpcicbu
PCI Host Mode PCI Agent Mode CardBus PC Card Host Mode CardBus PC Card Agent Mode 16-bit PC Card (PCMCIA) Host Mode
PCI_PCCDM = 0, PCI_HOSTM=1 PCI_PCCDM = 0, PCI_HOSTM=0 PCI_PCCDM = 1, PCI_HOSTM=1, CardBus PC Card is inserted PCI_PCCDM = 1, PCI_HOSTM=0 PCI_PCCDM = 1, PCI_HOSTM=1, 16-bit PC Card is inserted
NOTE: Each mode is selected by PCI_PCCDM & PCI_HOSTM pin input signal and inserted card type
1-32
S3C2510A
PRODUCT OVERVIEW
1.7 S3C2510A PCI & PC CARD I/O
Table 1-4. Cell Description Cell Name phtipcicbuc phopcicbc phtbpcicbuc phtbpcicbc phtbdpcicbuc phtipcicbup phopcicbp phtbpcicbup phtbpcicbp phtbdpcicbup phbcbcvs phicbccd Type (I/O/B/OD) I O B B B(OD) I O B B B(OD) B I for CVS[2:1] for CCD#[2:1] PCI ENCB =''0'' 66MHz Description CardBus PC Card (16-bit PC Card) Mode Condition ENCB =''1'' Operating Frequency 33MHz
1-33
PRODUCT OVERVIEW
S3C2510A
Table 1-5. PCI & PC Card Pull-up Description Pin Name I/O cell Ball Grid AA1 Y3 Int. Arb. Pull-up Pull-up Pull-up Pull-up Pull-up No Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up* AE22 AC21 AE21 AD20 AF20 AF22 AA25 AA24 Y26 Y25 Y24 W26 W25 W24 AE19 AF19 L25 PCI Host Mode PCI Agent Mode "0" "0" Int. Arb. No No No No No No No No No No No No No No No No No Pull-up Pull-up Pull-up Pull-up Pull-up No No Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up No Pull-up* No No No No No No Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up* CardBus Host Mode "1" "1" Ext. Arb. No No No No No No No Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up No Pull-up* No No No No No Pull-up Pull-up No No No No No No No No No No Pull-up Pull-up No No No No No No No No No No No Pull-up Pull-up Pull-up Pull-up CardBus Agent Mode "1" "0" PCMCIA Host Mode "1" "1"
PCI_PCCDM mode PCI_HOSTM mode PCIREQ1 PCIREQ2 PCIREQ3 PCIREQ4 PCIREQ5 PCIGNT1 PCIFRAME PCIIRDY PCITRDY PCIDEVSEL PCISTOP PCILOCK PCIPERR PCISERR PCIINTA PCIPME PCICLKRUN phtbpcicbu phtipcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbpcicbu phtbdpcicbu phtbdpcicbu phtbpcicbu phtbpcicbu
"0" "1" Ext. Arb.
Arbiter mode (PCICON[ARB])
NOTE: * pull-up is enabled only during clock stop mode.
1-34
S3C2510A
PRODUCT OVERVIEW
SYMBOL AND TRUTH TABLE
(note)
ENPU PAD Y PO PI
NOTE:
ENPU = 'low' Pull-up Enabled, ENPU = 'high' Pull-up Disabled. phtipcicb cell has a current path from VDD to PAD as following application. ENPU = low and PAD = low. The value of pull-up resistor is 35K[] in typical condition (Voltage: 3.3V, Process: NN, Temp: 25 C)
Figure 1-2. Symbol of phtipcicbu(c/p)
Table 1-6. Truth Table of phtipcicbu(c/p) PAD 1 0 1 PI 1 x 0 Y 1 0 1 PO 0 1 1
1-35
PRODUCT OVERVIEW
S3C2510A
(note)
(note)
ENPU TN EN A ENCB Y PO PI
ENPU TN EN PAD ENCB Y PO PI PAD
NOTE:
ENPU = 'low' & EN = 'high' Pull-up Enabled. Those cell have a current path from VDD to PAD as following application. (ENPU = low & EN = high) and PAD = low. The value of pull-up resistor is 35K[] in typical condition (Voltage: 3.3V, Process: NN, Temp: 25 C)
Figure 1-3. Symbol of phtbpcicbu(c/p) and phtbdpcicb(c/p)
Table 1-7. Truth Table (Input) of phtbpcicbu(c/p) and phtbdpcicb(c/p) PAD 1 0 1 PI 1 x 0 Y 1 0 1 PO 0 1 1
Table 1-8. Truth Table (Output) of phtbpcicbu(c/p) A 0 1 x x x EN 0 0 1 0 1 TN 1 1 x 0 0 ENPU x x 0 1 x 0 1 PAD 0 1 1 Hi-Z Hi-Z 1 Hi-Z
1-36
S3C2510A
PRODUCT OVERVIEW
Table 1-9. Truth Table (Open Drain) of phtbdpcicb(c/p) EN 0 1 0 1 TN 1 x 0 0 ENPU x 0 1 x 0 1 PAD 0 1 Hi-Z Hi-Z 1 Hi-Z
TN EN A ENCB Y PO PI
PAD
TN EN A ENCB
PAD

Figure 1-4. Symbol of phtbpcicb(c/p) and phopcicb(c/p)
Table 1-10. Truth Table (Input) of phtbpcicb(c/p) PAD 1 0 1 PI 1 x 0 Y 1 0 1 PO 0 1 1
Table 1-11. Truth Table (Output) of phtbpcicb(c/p) and phopcicb(c/p) A 0 1 x x EN 0 0 1 x TN 1 1 x 0 PAD 0 1 Hi-Z Hi-Z
1-37
PRODUCT OVERVIEW
S3C2510A
(note)
A PAD Y PO PI Y PO PI
PAD
NOTE:
Those cell have a current path from VDD to PAD when PAD is Low. The value of pull-up resistor is 130K[] in typical condition (Voltage: 3.3V, Process: NN, Temp: 25 C)
Figure 1-5. Symbol of phicbccd and phbcbcvs
1-38
S3C2510A
PRODUCT OVERVIEW
1.8 PIN ASSIGNMENT
Table 1-12. Pin Assignment Pin # B1 C2 C1 D2 D3 D1 E2 E4 E3 E1 F2 F4 F3 F1 G2 G1 G3 H2 H4 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 L1 MDC MDIO COL_0 TX_CLK_0 TXD0_0 TXD1_LOOP10_0 TXD2_0 TXD3_0 TX_EN_0 TX_ERR_PCOMP_10M_0 CRS_0 RX_CLK_0 RXD0_0 RXD1_0 RXD2_0 RXD3_0 RX_DV_LINK10_0 RX_ERR_0 COL_1 TX_CLK_1 TXD0_1 TXD1_LOOP10_1 TXD2_1 TXD3_1 TX_EN_1 TX_ERR_PCOMP_10M_1 CRS_1 RX_CLK_1 RXD0_1 RXD1_1 Pin Name Direction O B I I O O O O O O I I I I I I I I I I O O O O O O I I I I Pin # M2 M1 L3 N2 M4 N1 M3 P2 P1 N3 R2 P3 R1 T2 R3 T1 R4 U2 T3 U1 U4 V2 U3 V1 W2 W1 V3 Y2 W4 Y1 RXD2_1 RXD3_1 RX_DV_LINK10_1 RX_ERR_1 USB_CLKSEL USB_XCLK 1.8VDD_A USB_FILTER GND_A 1.8VDD_A FILTER GND_A 1.8VDD_A PHY_FILTER GND_A 1.8VDD_A PCI_FILTER GND_A XCLK CLKSEL SCL SDA PHY_CLKSEL HUSB_OVRCURRENT0 USB_DP USB_DN HUSB_OVRCURRENT1 PHY_FREQ HUSB_DP0 HUSB_DN0 I I B B I I B B I I B B O O O O Pin Name Direction I I I I I I
1-39
PRODUCT OVERVIEW
S3C2510A
Table 1-12. Pin Assignment (Continued) Pin # W3 AA2 AA4 AA1 Y3 AB2 AB1 AA3 AC2 AB4 AC1 AB3 AD2 AC3 AD1 AE1 AF2 AE3 AF3 AE4 AD4 AF4 AE5 AC5 AD5 AF5 AE6 AC6 AD6 AF6 BIG PCI_PCCDM HUSB_DP1 HUSB_DN1 PCI_HOSTM nRESET PCI_CLKSEL PCI_XCLK CLK_MOD0 CLK_MOD1 BUS_FREQ0 BUS_FREQ1 BUS_FREQ2 CPU_FREQ0 CPU_FREQ1 CPU_FREQ2 B0SIZE0 B0SIZE1 TMODE TMS TDO TDI nTRST TCK GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 Pin Name Direction I I B B I I I I I I I I I I I I I I I I O I I I B B B B B B Pin # AE7 AF7 AD7 AE8 AC8 AF8 AD8 AE9 AF9 AE10 AD9 AF10 AC10 AE11 AD10 AF11 AE12 AF12 AD11 AE13 AC12 AF13 AD12 AE14 AF14 AD13 AE15 AD14 AF15 AE16 GPIO6 GPIO7 GPIO8_xINT0 GPIO9_xINT1 GPIO10_xINT2 GPIO11_xINT3 GPIO12_xINT4 GPIO13_xINT5 GPIO14_xGDMA_Req0 GPIO15_xGDMA_Req1 GPIO16_xGDMA_Req2 GPIO17_xGDMA_Req3 GPIO18_xGDMA_Ack0 GPIO19_xGDMA_Ack1 GPIO20_xGDMA_Ack2 GPIO21_xGDMA_Ack3 GPIO22_TIMER0 GPIO23_TIMER1 GPIO24_TIMER2 GPIO25_TIMER3 GPIO26_TIMER4 GPIO27_TIMER5 PHY_CLKO GPIO28_HURXD0 GPIO29_HUTXD0 GPIO30_HUnDTR0 GPIO31_HUnDSR0 GPIO32_HUnRTS0 GPIO33_HUnCTS0 GPIO34_HUnDCD0 Pin Name Direction B B B B B B B B B B B B B B B B B B B B B B O B B B B B B B
1-40
S3C2510A
PRODUCT OVERVIEW
Table 1-12. Pin Assignment (Continued) Pin # AD15 AF16 AC15 AE17 AD16 AF17 AC17 AE18 AD17 AF18 AE19 AF19 AD18 AE20 AC19 AF20 AD19 AE21 AC21 AF21 AD20 AE22 AF22 AD21 AE23 AC22 AF23 AD22 AE24 AD23 UCLK GPIO35_HURXD1 GPIO36_HUTXD1 GPIO37_HUnDTR1 GPIO38_HUnDSR1 GPIO39_HUnRTS1 GPIO40_HUnCTS1 GPIO41_HUnDCD1 GPIO42_CURXD CUTXD PCIRST PCIINTA PCICLK3 PCIREQ4 PCIREQ5 PCIGNT4 PCIGNT5 PCIGNT2 PCIGNT1 PCIREQ3 PCIGNT3 PCIPME PCIREQ1 PCIREQ2 PCIAD28 PCIAD30 PCIAD29 PCIAD31 PCICLK2 PCIAD27 Pin Name Direction I B B B B B B B B O B B B B B O O B B B B B B I B B B B O B Pin # AF24 AF25 AE26 AD25 AD26 AC25 AC24 AC26 AB25 AB23 AB24 AB26 AA25 AA23 AA24 AA26 Y25 Y26 Y24 W25 W23 W26 W24 V25 V26 U25 V24 U26 U23 T25 PCIAD26 PCIAD25 PCIAD24 PCIAD23 PCICBE3 PCIAD21 PCIAD20 PCIAD22 PCIAD18 PCIAD16 PCIAD17 PCIAD19 PCIFRAME PCICLK1 PCIIRDY PCICBE2 PCIDEVSEL PCITRDY PCISTOP PCIPERR PCIPAR PCILOCK PCISERR PCIAD15 PCICBE1 PCIAD12 PCIAD14 PCIAD13 PCIAD10 PCIAD8 Pin Name Direction B B B B B B B B B B B B B O B B B B B B B B B B B B B B B B
1-41
PRODUCT OVERVIEW
S3C2510A
Table 1-12. Pin Assignment (Continued) Pin # U24 T26 R25 R26 T24 P25 R23 P26 R24 N25 N26 P24 M25 N24 M26 L25 M24 L26 M23 K25 L24 K26 K23 J25 K24 J26 H25 H26 J24 G25 PCIAD11 PCIAD9 PCIAD6 PCIAD7 PCICBE0 PCIAD2 PCIAD4 PCIAD3 PCIAD5 PCICVS2 PCIAD0 PCIAD1 PCICCD1 PCICVS1 PCICCD2 PCICLKRUN XBMREQ XBMACK HCLKO nEWAIT CKE nMCS0 nMCS1 nMCS2 nMCS3 nMCS4 nMCS5 nMCS6 nMCS7 nOE Pin Name Direction B B B B B B B B B B B B I B I B I O B I O O O O O O O O O O Pin # H23 G26 H24 F25 F23 F26 G24 E25 E26 F24 D25 E23 D26 E24 C25 D24 C26 B26 A25 B24 A24 B23 C23 A23 B22 D22 C22 A22 B21 D21 Pin Name nWBE0/DQM0 nWBE1/DQM1 nWBE2/DQM2 nWBE3/DQM3 nSDWE nSDCS0 nSDCS1 nSDRAS nSDCAS XDATA0 XDATA1 XDATA2 XDATA3 XDATA4 XDATA5 XDATA6 XDATA7 XDATA8 XDATA9 XDATA10 XDATA11 XDATA12 XDATA13 XDATA14 XDATA15 XDATA16 XDATA17 XDATA18 XDATA19 XDATA20 Direction O O O O O O O O O B B B B B B B B B B B B B B B B B B B B B
1-42
S3C2510A
PRODUCT OVERVIEW
Table 1-12. Pin Assignment (Continued) Pin # C21 A21 B20 A20 C20 B19 D19 A19 C19 B18 A18 B17 C18 A17 D17 B16 C17 A16 B15 A15 C16 B14 D15 A14 C15 B13 A13 C14 B12 C13 XDATA21 XDATA22 XDATA23 XDATA24 XDATA25 XDATA26 XDATA27 XDATA28 XDATA29 XDATA30 XDATA31 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 Pin Name Direction B B B B B B B B B B B O O O O O O O O O O O O O O O O O O O Pin # A12 B11 C12 A11 D12 B10 C11 A10 D10 B9 C10 A9 B8 A8 C9 B7 D8 A7 C8 B6 D6 A6 C7 B5 A5 C6 B4 D5 A4 C5 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 GPIO43_UTO_TXAD0 GPIO44_UTO_TXAD1 GPIO45_UTO_TXAD2 UTO_RXAD0 UTO_RXAD1 UTO_RXAD2 GPIO46_UTO_TXD0 GPIO47_UTO_TXD1 GPIO48_UTO_TXD2 GPIO49_UTO_TXD3 GPIO50_UTO_TXD4 GPIO51_UTO_TXD5 GPIO52_UTO_TXD6 GPIO53_UTO_TXD7 GPIO54_UTO_TXSOC UTO_CLK GPIO55_UTO_TXENB UTO_TXCLAV GPIO56_UTO_RXD0 GPIO57_UTO_RXD1 GPIO58_UTO_RXD2 GPIO59_UTO_RXD3 GPIO60_UTO_RXD4 GPIO61_UTO_RXD5 GPIO62_UTO_RXD6 Pin Name Direction O O O O O B B B O O O B B B B B B B B B O B I B B B B B B B
1-43
PRODUCT OVERVIEW
S3C2510A
Table 1-12. Pin Assignment (Continued) Pin # B3 C4 A3 A2 G4 T4 AC7 AC16 Y23 L23 D20 D11 L4 Y4 AC11 AC20 T23 G23 D16 D7 A1 J4 AF1 AC9 AC23 V23 D23 D18 B2 N4 Pin Name GPIO63_UTO_RXD7 UTO_RXSOC UTO_RXENB UTO_RXCLAV 3.3VDD 3.3VDD 3.3VDD 3.3VDD 3.3VDD 3.3VDD 3.3VDD 3.3VDD 1.8VDD 1.8VDD 1.8VDD 1.8VDD 1.8VDD 1.8VDD 1.8VDD 1.8VDD GND GND GND GND GND GND GND GND GND GND Direction B I O I Pin # AE2 AC13 AD24 P23 C24 D14 C3 P4 AD3 AC14 AE25 N23 B25 D13 D4 V4 AC4 AC18 AF26 J23 A26 D9 K10 L10 M10 N10 P10 R10 T10 U10 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Name Direction
1-44
S3C2510A
PRODUCT OVERVIEW
Table 1-12. Pin Assignment (Continued) Pin # K11 L11 M11 N11 P11 R11 T11 U11 K12 L12 M12 N12 P12 R12 T12 U12 K13 L13 M13 N13 P13 R13 T13 U13 K14 L14 M14 N14 P14 R14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Name Direction Pin # Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction
T14 U14 K15 L15 M15 N15 P15 R15 T15 U15 K16 L16 M16 N16 P16 R16 T16 U16 K17 L17 M17 N17 P17 R17 T17 U17
1-45
PRODUCT OVERVIEW
S3C2510A
1.9 PIN ASSIGNMENT FIGURE
A1 CORNER
1 2 3 4 5 6 7 8 9
S3C2510 416PBGA2727 TOP VIEW
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A B C D E F G H J K L M N P R T U V W Y
AA AB AC AD AE AF
GND
UTO_RX UTO_RX CLAV ENB
GPIO61 GPIO57 GPIO55 GPIO52 GPIO48 GPIO46 GPIO45 _UTO _UTO _UTO _UTO _UTO _UTO _UTO ADDR22 ADDR19 ADDR15 ADDR12 ADDR8 _RXD5 _RXD1 _TXENB _TXD6 _TXD2 _TXD0 _TXAD2
ADDR6
ADDR2
XDATA3 XDATA2 XDATA2 XDATA2 XDATA1 XDATA1 XDATA1 XDATA9 1 8 4 2 8 4 1 XDATA3 XDATA2 XDATA2 XDATA1 XDATA1 XDATA1 XDATA1 0 6 3 9 5 2 0 XDATA2 XDATA2 XDATA2 XDATA1 XDATA1 ADDR1 9 5 1 7 3 XDATA2 XDATA2 XDATA1 3.3VDD 7 0 6
GND
A B C D E F G H J K L M N P R T U V W Y
AA AB AC AD AE AF
MDC
GND
GPIO63 GPIO59 GPIO56 GPIO54 GPIO50 GPIO47 GPIO43 UTO _UTO _UTO _UTO _UTO _UTO _UTO _UTO ADDR20 ADDR17 ADDR14 ADDR10 ADDR7 _RXAD1 _RXD7 _RXD3 _RXD0 _TXSOC _TXD4 _TXD1 _TXAD0 GND
ADDR4
ADDR0
GND
XDATA8
COL_0
MDIO
GPIO62 GPIO58 GPIO53 GPIO49 GPIO44 UTO UTO_TX UTO _UTO _UTO _UTO _UTO _UTO ADDR21 ADDR18 ADDR16 ADDR13 ADDR9 _RXSOC CLAV _RXAD2 _RXD6 _RXD2 _TXD7 _TXD3 _TXAD1 UTO _CLK GPIO51 1.8VDD _UTO _TXD5 GND UTO 3.3VDD ADDR23 _RXAD0 GND GND ADDR11 1.8VDD
ADDR5
GND
XDATA5 XDATA7
TXD1_L GPIO60 TX_CLK OOP10_ _UTO TXDO_0 GND _0 0 _RXD4 TX_ERR _PCOM TX_EN_ TXD2_0 TXD3_0 P_10M_ 0 0 RX_CLK RXD1_0 CRS_0 RXD0_0 _0 RX_DV_ RXD3_0 RXD2_0 LINK10_ 3.3VDD 0 TX_CLK RX_ERR TXD0_1 COL_1 _1 _0 TXD1_L TX_EN_ TXD2_1 OOP10_ GND 1 1 TX_ERR _PCOM TXD3_1 RXD0_1 CRS_1 P_10M_ 1 RX_DV_ RX_CLK LINK10_ 1.8VDD RXD1_1 _1 1 1.8VDD_ USB_CL RXD3_1 RXD2_1 A KSEL USB_XC RX_ERR 1.8VDD_ LK _1 A USB_FIL GND_A GND_A TER 1.8VDD_ FILTER GND_A A 1.8VDD_ PHY_FIL A TER
ADDR3
GND
GND
XDATA6 XDATA1 XDATA3
XDATA2 XDATA4 nSDRAS nSDCAS
nWBE3/ nSDWE XDATA0 nSDCS0 DQM3 nWBE1/ DQM1
1.8VDD nSDCS1
n0E
nWBE0/ nWBE2/ nMCS5 DQM0 DQM2
nMCS6
GND
nMCS7
nMCS2
nMCS4
GND
GND
GND
GND
GND
GND
GND
GND
nMCS1
nMCS3 nEWAIT nMCS0
GND
GND
GND
GND
GND
GND
GND
GND
3.3VDD
CKE
PCICLK XBMAC RUN K
GND
GND
GND
GND
GND
GND
GND
GND
XBMRE PCICCD PCICCD HCLKO Q 1 2 PCICVS PCICVS PCIAD0 1 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCIAD1 PCIAD2 PCIAD3
PCI_ FILTER
GND
GND
GND
GND
GND
GND
GND
GND
PCIAD4 PCIAD5 PCIAD6 PCIAD7
XCLK
3.3VDD
GND
GND
GND
GND
GND
GND
GND
GND
1.8VDD
PCICBE PCIAD8 PCIAD9 0
PHY_CL CLKSEL GND_A KSEL HUSB_O VRCUR RENT0 HUSB_O VRCUR RENT1 BIG
SCL
GND
GND
GND
GND
GND
GND
GND
GND
PCIAD1 PCIAD1 PCIAD1 PCIAD1 0 1 2 3 PCIAD1 PCIAD1 PCICBE 4 5 1 PCISER PCIPER PCILOC R R K
SDA
GND
GND
USB_DN USB_DP
HUSB_D P0
PCIPAR
HUSB_D PHY_FR PCI_HO 1.8VDD N0 EQ STM HUSB_D PCI_PC PCI_XC HUSB_D N1 CDM LK P1 PCI_CL BUS_FR CLK_MO nRESET KSEL EQ1 D1 BUS_FR CLK_MO CPU_FR EQ0 D0 EQ0 CPU_FR BUS_FR EQ1 EQ2 CPU_FR EQ2 GPIO10 3.3VDD _xINT2 GPIO18 GPIO26 _xGDMA 1.8VDD _TIMER _Ack0 4 GPIO36 GPIO40 _HUTXD 3.3VDD _HUnCT 1 S1 UCLK PCIREQ PCIGNT PCIAD3 1.8VDD 5 1 0
PCISTO PCIDEV PCITRD 3.3VDD P SEL Y PCICLK PCIFRA PCICBE PCIIRDY 1 ME 2 PCIAD1 PCIAD1 PCIAD1 PCIAD1 6 7 8 9 PCIAD2 PCIAD2 PCIAD2 0 1 2 PCIAD2 PCICBE 3 3 PCIAD2 4
GND
TCK
GPIO3
GND
GND
GND
GND
GND
GND
TD0
GPIO0
GPIO16 GPIO20 GPIO24 GPIO8_x GPIO12 _xGDMA _xGDMA _TIMER GPIO4 INT0 _xINT4 _Req2 _Ack2 2 GPIO2 GPIO6 GPIO9 _xINT1
GPIO30 GPIO32 PHY _HUnDT _HUnRT _CLK0 R0 S0
GPIO38 GPIO42 PCICLK PCIGNT PCIGNT PCIREQ PCIAD3 PCIAD2 _HUnDS _CURXD 3 5 3 2 1 7 R1
GND
GND
BOSIZE 1
TMS
nTRST
GPIO15 GPIO19 GPIO22 GPIO25 GPIO28 GPIO31 GPIO34 GPIO37 GPIO41 GPIO13 PCIREQ PCIGNT PCIAD2 PCICLK _xGDMA _xGDMA _TIMER _TIMER _HURXD _HUnDS _HUnDC _HUnDT _HUnDC PCIRST PCIPME _xINT5 4 2 8 2 _Req1 _Ack1 0 3 0 R0 D0 R1 D1
GND
GND
BOSIZE TMODE 0
TD1
GPIO1
GPIO5
GPIO7
GPIO14 GPIO17 GPIO21 GPIO23 GPIO27 GPIO29 GPIO33 GPIO35 GPIO39 GPIO11 PCIGNT PCIREQ PCIREQ PCIAD2 PCIAD2 PCIAD2 _xGDMA _xGDMA _xGDMA _TIMER _TIMER _HUTXD _HUnCT _HURXD _HUnRT CUTXD PCIINTA _xINT3 4 3 1 9 6 5 _Req0 _Req3 _Ack3 1 5 0 S0 1 S1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 1-6. Pin Assignment Figure
1-46

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